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SY89540U
Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination
General Description
The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates up to 3.2Gbps over temperature and voltage. The SY89540U differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The LVDS compatible outputs maintain extremely fast rise/fall times guaranteed to be less than 120ps. The SY89540U features a patent-pending isolation design that significantly improves on channel-tochannel crosstalk performance. The SY89540U operates from a 2.5V 5% supply and is guaranteed over the full industrial temperature range (-40C to +85C). The SY89540U is part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at www.micrel.com.
Precision Edge(R)
Features
* Provides crosspoint switching between any input pairs to any output pair * Patent pending, channel-to-channel isolation design provides superior crosstalk performance * Guaranteed AC performance over temperature and voltage: * DC-to-3.2Gbps throughput - <480ps propagation delay - <120ps rise/fall time - <30ps output-to-output skew * Ultra-low jitter design: - <1psRMS random jitter - <10psPP deterministic jitter - <10psPP total jitter (clock) - <0.7psRMS crosstalk induced jitter * Patent pending 50 input termination, extended CMVR, and VT pin accepts DC- and AC-coupled differential inputs * 350mV LVDS output swing * Power supply 2.5V 5% * -40C to +85C temperature range * Available in 44-pin (7mm x 7mm) MLFTM package * Pb-Free Green package
Typical Performance
2.5Gbps Output
OUTPUT SWING (100mV/div.)
Applications
* All SONET/SDH channel select applications * All Fibre Channel multi-channel select applications * All Gigabit Ethernet multi-channel select applications
TIME (100ps/div.)
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
April 2005
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SY89540U
Functional Block Diagram
I N0
50
VT0
50
0 1 2 3 Q0 /Q 0
/I N0 Vref_AC0
I N1
50
0 1 2 3 Q1 /Q 1
VT1
50
/I N1 Vref_AC1
0
I N2
50
1 2 3
Q2 /Q 2
VT2
50
/I N2 Vref_AC2
0 1
I N3
50
Q3 /Q 3
2 3
VT3
50
/I N3 Vref_AC3 SIN0 (CMOS/TTL ) SIN1 (CMOS/TTL ) SOUT0 (CM OS/TTL ) SOUT1 (CM OS/TTL ) CONF (CM OS/TTL) L OAD (CMOS/TTL )
CO NT RO L
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SY89540U
Ordering Information(1)
Part Number SY89540UMI SY89540UMITR SY89540UMG SY89540UMGTR(2) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electrical only. 2. Tape and Reel ordering option.
(2)
Package Type MLF-44 MLF-44 MLF-44 MLF-44
Temperature Range Industrial Industrial Industrial Industrial
Package Marking 89540U 89540U 89540U with Pb-Free bar-line indicator 89540U with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
Pin Configuration
GND GND VREF_AC3 IN3 VT3 /IN3 SOUT0 SOUT1 GND GND VCC
VREF_AC2 /IN2 VT2 IN2 CONFIG VCC LOAD /IN1 VT1 IN1 VREF_AC1
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22
GND GND VREF_AC0 /IN0 VT0 IN0 SIN0 SIN1 GND GND VCC
/Q3 Q3 VCC /Q2 Q2 VCC /Q1 Q1 VCC /Q0 Q0
44-Pin MLFTM (MLF-44)
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SY89540U
Pin Description
Pin Number 17, 15, 10, 8 4, 2 41, 39 16, 9, 3, 40 Pin Name IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3 VT0, VT1, VT2, VT3 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50 . Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. Reference Voltage: This output biases to VCC-1.2V. It is used when ACcoupling the inputs (IN, /IN). Connect VREF_AC to the VT pin. Bypass each VREF-AC pin with a 0.01F low ESR capacitor. See "Input Interface Applications" section for more details. These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs are internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. These single-ended TTL/CMOS-compatible inputs control the transfer of the addresses to the internal multiplexers. See "Address Tables" and "Timing Diagram" sections for more details. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open.
14, 11, 1, 42 18, 19
VREF_AC0, VREF_AC1, VREF_AC2, VREF_AC3 SIN0, SIN1 SOUT0, SOUT1 CONF, LOAD
38, 37
5, 7
Configuration Sequence
1. Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration. 2. Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration.
Buffer Mode
The SY89540U defaults to buffer mode (IN to Q) if the load and configuration control signals are not exercised. 23, 24, 26, 27, 29, 30, 32, 33 6, 22, 25, 28, 31, 34 12, 13, 20, 21,35, 36, 43, 44 Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, VCC GND, Exposed pad Differential Outputs: These LVDS output pairs are the outputs of the device. Please refer to the truth table below for details. Unused output pairs may be left open. Each output is designed to drive 350mV into 100 across the pair. Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors and place as close to each VCC pin. Ground. GND and EPad must both be connected to the same ground.
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SY89540U
Absolute Maximum Ratings(1)
Supply Voltage (VCC)............................. -0.5V to +4.0V Input Voltage (VIN)..................................... -0.5V to VCC CML Output Voltage (VOUT) .......VCC-1.0V to VCC+5.0V Termination Current(3) Source or sink current on VT..................... 100mA Input Current Source or sink current on IN, /IN................ 50mA VREF-AC Current Source or sink current on VREF-AC ................. 2mA Lead Temperature (soldering, 20sec.)............... 260C Storage Temperature (Ts) .................-65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ....................+2.375V to +2.625V Ambient Temperature (TA) .................. -40C to +85C Package Thermal Resistance(4) MLFTM ( JA) Still-air ............................................................... 23C/W MLFTM ( JB) Junction-to-board.............................................. 12C/W
DC Electrical Characteristics(5)
TA = -40C to +85C, unless otherwise noted.
Symbol VCC ICC RDIFF_IN RIN VIH VIL VIN VDIFF_IN IN-to-VT VREF-AC Notes: 1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Due to limited drive capability use for input of the same package only. Assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JA in still-air unless otherwise stated.
JB
Parameter Power Supply Power Supply Current Differential Input Resistance (IN-to-/IN) Input Resistance (IN-to-VT, /IN-to-VT) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage |IN, /IN| Maximum Input Voltage |IN-to-VT| Reference Voltage
Condition VCC = 2.5V No load, max. VCC.
Min 2.375 80 40
Typ 2.5 200 100 50
Max 2.625 280 120 60 VCC VIH-0.1 1700
Units V mA
Note 6
VCC-1.6 0
V V mV mV
See Figure 1a. See Figure 1b.
100 200
1.28 VCC-1.3 VCC-1.2 VCC-1.1
V V
2. 3. 4. 5. 6.
uses a 4-layer
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. VIH (min) not lower than 1.2V.
April 2005
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SY89540U
LVDS Outputs DC Electrical Characteristics
VCC = 2.5V 5%, TA = -40C to +85C, RL = 100
Symbol VOH VOL VOUT VDIFF_OUT VOCM VOCM Parameter Output HIGH Voltage (Q, /Q) Output LOW Voltage (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing |Q - /Q| Output Common Mode Voltage (Q, /Q) Change in Common Mode Voltage (Q, /Q) See Figure 1a. See Figure 1b. See Figure 4b. See Figure 4b. 0.925 250 500 1.125 -50 350 700 1.275 +50
across Q and /Q, unless otherwise noted.
Min Typ Max 1.475 Units V V mV mV V mV
Condition
LVTTL/CMOS DC Electrical Characteristics
VCC = 2.5V 5%, TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VIL = 0V -125 -300 Condition Min 2.0 Typ Max VCC 0.8 30 Units V V A A
April 2005
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SY89540U
AC Electrical Characteristics(7)
VCC = 2.5V 5%, TA = -40C to +85C, RL = 100
Symbol fMAX tPD Parameter Maximum Operating Frequency Propagation Delay
across each output pair, unless otherwise noted.
Min 3.2 280 350 160 Typ 4 4 380 480 800 fs/C Max Units Gbps GHz
Condition NRZ Data Clock, VOUT 200mV IN-to-Q CONFIG-to-Q
tPD Tempco tS Set-up Time SIN-to-LOAD SOUT-to-LOAD LOAD-to-CONFIG CONFIG-to-LOAD Hold Time LOAD-to-SIN, LOAD-to-SOUT Minimum LOAD and CONFIG Pulse Width Output-to-Output Skew Part-to-Part Skew Data Random Jitter (RJ) Deterministic Jitter (DJ) Clock Cycle-to-Cycle Jitter Total Jitter (TJ) Crosstalk-Induced Jitter tr, tr Notes: 7. 8. 9. High frequency AC-parameters are guaranteed by design and characterization. Rise/Fall Times Note 8 Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 At full output swing (20% to 80%) 40 800 800 800 950 800 800
ps
th tPW tSKEW tJITTER
ps ps 30 150 1 10 1 0.7 80 120 ps ps psRMS psPP psRMS psPP psRMS ps
Output to output skew is measured between two different outputs under identical transitions. Input voltage swing is 100mV. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
10. RJ is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps/3.2Gbps. 11. DJ is measured at 2.5Gbps/3.2Gpbs, with both K28.5 and 223-1 PRBS pattern 12. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn -Tn-1 where T is the time between rising edges of the output signal. 13. TJ definition: with an ideal clock input of frequency < fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 14. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs.
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SY89540U
Single-Ended and Differential Swing
VIN, VOUT 350mV (typical)
VDIFF_IN, VDIFF_OUT 700mV (typical)
Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing
Timing Diagram
Input Address SIN[1:0]
Output Address SOUT[1:0] t s (SIN-LOAD) LOAD t s (SOUT-LOAD) t PW t h (LOAD-SIN/SOUT) t s (CONFIG-LOAD)
CONFIG /IN[3:0] IN[3:0] t PD /Q[3:0]
t s (LOAD-CONFIG)
t PW
t PD (CONFIG-Q)
Invalid** Q[3:0]
Valid**
**Invalid and Valid refers to configuration being changed. All outputs with unchanged configuration remain valid.
Figure 2. Timing Diagram
Truth Tables
Input Select Address Table SIN1 0 0 1 1 SIN0 0 1 0 1 Input IN0 IN1 IN2 IN3 0 0 1 1 Output Select Address Table SOUT1 SOUT0 0 1 0 1 Output Q0 Q1 Q2 Q3
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SY89540U
Typical Operating Characteristics
VCC = 2.5, VIN = 100mV, at 25C.
OUTPUT PROPAGATION DELAY (ps)
350 300
Amplitude vs. Frequency
PROPAGATION DELAY (ps)
370 365 360 355 350
Propagation Delay vs. Temperature
370 365 360 355 350 345 340
Input Voltage Swing vs. Propagation Delay
AMPLITUDE (ps)
250 200 150 100
1400
2000
2600
3200
3800
4400
5000
5600
TEMPERATURE (C)
FREQUENCY (MHz)
INPUT VOLTAGE SWING (ps)
CHANNEL-to-CHANNEL SKEW (ps)
16 14 12 10 8 6 4 2 0 0
Channel-to-Channel Skew, Relative to Ch0
1
2 CHANNEL (ps)
3
4
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1000
200
800
100
200
300
400
500
600
700
800
900
50
345 -40 -20 0
20 40 60 80 100 120
335
Micrel, Inc.
SY89540U
Functional Characteristics
VCC = 2.5, VIN = 100mV, at 25C.
Clock Pattern
200MHz Output
OUTPUT SWING (80mV/div.) OUTPUT SWING (80mV/div.)
1.25GHz Output
TIME (600ps/div.) 2.5GHz Output
OUTPUT SWING (80mV/div.)
TIME (100ps/div.)
TIME (50ps/div.)
Data Pattern
1.25Gbps Output
OUTPUT SWING (100mV/div.) OUTPUT SWING (100mV/div.)
3.2Gbps Output
TIME (200ps/div.)
TIME (80ps/div.)
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SY89540U
Input and Output Stage Internal Termination
VCC
Output Stage Internal Termination
On a nominal 1.25V common mode above ground, LVDS specifies a small swing of 350mV, typical. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum to keep EMI low.
IN
VOUT
50 VT 50 /IN GND
100 1%
VOH, VOL
VOH, VOL
GND
Figure 4a. LVDS Differential Measurement
Figure 3. Simplified Differential Input Stage
50 VCOM VCOM
50
GND
Figure 4b. LVDS Common Mode Measurement
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SY89540U
Input Interface Applications
VCC
VCC
VCC
IN
LVPECL
IN
LVPECL
IN CML /IN
VCC GND RP 0.1F
/IN SY89540U VT NC VREF-AC
Note: For 3.3V, RP = 50. For 2.5V, RP = 19.
/IN RP GND GND RP VCC 0.1F VT VREF-AC
Note: For 3.3V, RP = 100. For 2.5V, RP = 50.
SY89540U
GND NC NC VT
SY89540U
VREF-AC
Figure 5a. LVPECL Interface (DC-Coupled)
Figure 5b. LVPECL Interface (AC-Coupled)
Figure 5c. CML Interface (DC-Coupled)
VCC
VCC
IN CML /IN VCC GND 0.1F VT VREF-AC
Figure 5d. CML Interface (AC-Coupled)
IN LVDS /IN
SY89540U
GND NC NC VT
SY89540U
VREF-AC
Figure 5e. LVDS Interface
Related Product and Support Documentation
Part Number SY58540U HBW Solutions Function Ultra Precision 4x4 CML Crosspoint Switch w/Internal I/O Termination New Products and Applications MLFTM Application Note Data Sheet Link http:///www.micrel.com/product-info/products/sy89540u.shtml www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLF_AppNote.pdf
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SY89540U
Package Information
44-Pin MLFTM (MLF-44)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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